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<div class="title">tft Documentation</div>  </div>
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<div class="textblock"><p>This header file contains the definitions and declarations for the high level driver to access the Xilinx TFT Controller Device. The device has the capability of displaying data onto a 640*480 VGA TFT screen. It can take up to 256K colors. There is no interrupt mode.</p>
<p>The functions XTft_Setpixel and XTft_Getpixel are provided in the driver to write to and read from the individual pixels, the color values.</p>
<p>These are generally stored in the assigned 2MB Video Memory which is configurable.</p>
<p>Video Memory stores each pixel value in 32bits. Out of this 2MB memory which can hold 1024 pixels per line and 512 lines per frame data, only 640 pixels per line and 480 lines per frame are used.</p>
<p>Each base color Red, Green, Blue is encoded using 6 bits which sums up to 18bits which is stored in the Dual port BRAM.</p>
<p><b>Initialization &amp; Configuration</b></p>
<p>The <a class="el" href="struct_x_tft___config.html" title="This structure holds the Device base address, video memory base address and Unique identifier of the ...">XTft_Config</a> structure is used by the driver to configure itself. This configuration structure is typically created by the tool-chain based on HW build properties.</p>
<p>To support multiple runtime loading and initialization strategies employed by various operating systems, the driver instance can be initialized as follows:</p>
<ul>
<li>XTft_CfgInitialize(InstancePtr, CfgPtr, BaseAddress) - Uses a configuration structure provided by the caller. If running in a system with address translation, the provided virtual memory base address replaces the physical address present in the configuration structure.</li>
</ul>
<p><b>Interrupts</b></p>
<p>The TFT device supports a single interrupt which is generated for a Vsync pulse.</p>
<p>This driver does not provide a Interrupt Service Routine (ISR) for the device. It is the responsibility of the application to provide one if needed.</p>
<p><b>RTOS Independence</b></p>
<p>This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads or thread mutual exclusion, virtual memory, or cache control must be satisfied by the layer above this driver.</p>
<pre>
  MODIFICATION HISTORY:</pre><pre>  Ver    Who   Date      Changes
  -----  ----  --------  -----------------------------------------------
  1.00a  sg    03/24/08  First release
  2.00a	 ktn   07/06/09	 Added <a class="el" href="group__tft__v5__0.html#ga3241465696077377ea4000f4caca21a7" title="This function enables the Vsync Interrupt in the Interrupt Enable and Status Register. ">XTft_IntrEnable()</a>, <a class="el" href="group__tft__v5__0.html#ga1bc1f7d9c152c6e661cd125f4c190dd8" title="This function disables the Vsync Interrupt in the Interrupt Enable and Status Register. ">XTft_IntrDisable()</a>and,
			 <a class="el" href="group__tft__v5__0.html#gacc8325682d029d3618ff0a7d6ee265dc" title="This function gets the Vsync(Video address latch) status from the Interrupt Enable and Status Registe...">XTft_GetVsyncStatus()</a> functions to access newly added
			 Interrupt Enable and Status Register.
  3.00a  ktn   10/22/09  Updated driver to use the HAL APIs/macros.
		         Removed the macros XTft_mSetPixel and XTft_mGetPixel.
  3.00a  bss   01/16/12  Updated driver to remove warnings from asserts.
  3.01a  sg    05/30/12  Corrected the brace error introduced in
			 XTft_GetPixel while changing it from macro to
			 function for CR 647750.
  3.02a  bss   11/30/12  CR 690338 - Corrected the brace error introduced in
			 XTft_GetPixel for CR 647750.
  4.00a  bss   01/25/13	 Added support for AXI TFT controller, this driver
			 can only be used for AXI TFT controller
			 XTft_WriteReg and XTft_ReadReg functions are updated
			 Removed all functionality associated with DCR access
			 PlbAccess and DcrBaseAddr are removed from the
			 <a class="el" href="struct_x_tft___config.html" title="This structure holds the Device base address, video memory base address and Unique identifier of the ...">XTft_Config</a> config structure
  4.01a  bss   11/01/13	 Modified driver tcl to retrieve C_BASEADDR/C_HIGHADDR
			 CR#757359.
  5.0   adk  19/12/13 Updated as per the New Tcl API's
  6.0    sd  19/08/15  Updated the BaseAddress and VideoMemBaseAddr
		         variables in <a class="el" href="struct_x_tft___config.html" title="This structure holds the Device base address, video memory base address and Unique identifier of the ...">XTft_Config</a> to be UINTPTR to support
			 64 bit addresses. Added AddrWidth to the
			 <a class="el" href="struct_x_tft___config.html" title="This structure holds the Device base address, video memory base address and Unique identifier of the ...">XTft_Config</a> structure which reflects the value of
			 C_M_AXI_ADDR_WIDTH.
			 Updated to tcl add the C_M_AXI_ADDR_WIDTH  parameter.
			 Added XTFT_AR_LSB_OFFSET and XTFT_AR_MSB_OFFSET
			 definitions to the <a class="el" href="xtft__hw_8h.html">xtft_hw.h</a> file, these offsets
			 are valid only when the Address Width is greater
			 than 32 bits.
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